1. Field of the Invention
The present invention is related to the field of electronics. In particular, the present invention is related to a method and apparatus to execute instructions in a processor.
2. Description of the Related Art
Out-of-order processors commonly use a pipelining technique wherein multiple instructions are overlapped in execution in an effort to improve the overall performance of the processor e.g., a microprocessor. Pipelining is a technique that exploits parallelism among the processor instructions in a sequential instruction stream. Pipelining increases the processor's instruction throughput, without reducing the execution time of an individual instruction. This allows for a processor to execute a program faster with a lower total execution time, even though no single instruction runs faster.
In a pipelined processor, the latency from scheduling an instruction to executing the instruction, and then confirming the instruction executed correctly may be significantly longer than the latency of the instruction. Therefore, to minimize the effective latency of the instruction, dependent instructions should be scheduled before confirming that the first instruction executed correctly. In a pipelined processor, a scheduler speculatively schedules instructions assuming that all instructions will execute properly (e.g., all load instructions will hit in data cache). Thus, a situation may arise that prevents the next instruction in the instruction stream from executing correctly during its designated clock cycle if the instruction requires the results of the previous instruction in order for it to execute correctly. When this occurs, the processor must determine which instructions have not executed properly, either because the instruction was not able to generate the correct result given the correct input values, or the instruction could not generate the correct result because it was not provided with the correct input values.